#ifndef RXE_OPCODE_H
#define RXE_OPCODE_H

/*************************rxe_wr_opcode*************************/
enum rxe_wr_mask {
    //(UL(1) << (nr)) bit.h
    WR_INLINE_MASK  = BIT(0), //1
    WR_ATOMIC_MASK  = BIT(1), //2
    WR_SEND_MASK    = BIT(2), //4
    WR_READ_MASK    = BIT(3), //8
    WR_WRITE_MASK   = BIT(4), //16
    WR_LOCAL_OP_MASK = BIT(5), //32
    //WR_REG_MASK     = BIT(6), //64

    WR_READ_OR_WRITE_MASK       = WR_READ_MASK | WR_WRITE_MASK,
    WR_READ_WRITE_OR_SEND_MASK  = WR_READ_OR_WRITE_MASK | WR_SEND_MASK,
    WR_WRITE_OR_SEND_MASK       = WR_WRITE_MASK | WR_SEND_MASK,
    WR_ATOMIC_OR_READ_MASK      = WR_ATOMIC_MASK | WR_READ_MASK,
};

#define WR_MAX_QPT      (8)
struct rxe_wr_opcode_info {
    char    *name;
    enum rxe_wr_mask     mask[WR_MAX_QPT];
};

extern struct rxe_wr_opcode_info rxe_wr_opcode_info[];

/***********************rxe_opcode******************************/
enum rxe_hdr_type {
    RXE_LRH,//0
    RXE_GRH,//1
    RXE_BTH,//2
    RXE_RETH,//3
    RXE_AETH,//4
    RXE_ATMETH,//5
    RXE_ATMACK,//6
    RXE_IETH,//7
    RXE_RDETH,//8
    RXE_DETH,//9
    RXE_IMMDT,//10
    RXE_PAYLOAD,//11
    NUM_HDR_TYPES//12
};

enum rxe_hdr_mask {
    RXE_LRH_MASK        = BIT(RXE_LRH),
    RXE_GRH_MASK        = BIT(RXE_GRH),
    RXE_BTH_MASK        = BIT(RXE_BTH),
    RXE_IMMDT_MASK      = BIT(RXE_IMMDT),
    RXE_RETH_MASK       = BIT(RXE_RETH),
    RXE_AETH_MASK       = BIT(RXE_AETH),
    RXE_ATMETH_MASK     = BIT(RXE_ATMETH),
    RXE_ATMACK_MASK     = BIT(RXE_ATMACK),
    RXE_IETH_MASK       = BIT(RXE_IETH),
    RXE_RDETH_MASK      = BIT(RXE_RDETH),
    RXE_DETH_MASK       = BIT(RXE_DETH),
    RXE_PAYLOAD_MASK    = BIT(RXE_PAYLOAD),

    RXE_REQ_MASK        = BIT(NUM_HDR_TYPES + 0),
    RXE_ACK_MASK        = BIT(NUM_HDR_TYPES + 1),
    RXE_SEND_MASK       = BIT(NUM_HDR_TYPES + 2),
    RXE_WRITE_MASK      = BIT(NUM_HDR_TYPES + 3),
    RXE_READ_MASK       = BIT(NUM_HDR_TYPES + 4),
    RXE_ATOMIC_MASK     = BIT(NUM_HDR_TYPES + 5),

    RXE_RWR_MASK        = BIT(NUM_HDR_TYPES + 6),
    RXE_COMP_MASK       = BIT(NUM_HDR_TYPES + 7),

    RXE_START_MASK      = BIT(NUM_HDR_TYPES + 8),
    RXE_MIDDLE_MASK     = BIT(NUM_HDR_TYPES + 9),
    RXE_END_MASK        = BIT(NUM_HDR_TYPES + 10),

    RXE_LOOPBACK_MASK   = BIT(NUM_HDR_TYPES + 12),

    RXE_READ_OR_ATOMIC  = (RXE_READ_MASK | RXE_ATOMIC_MASK),
    RXE_WRITE_OR_SEND   = (RXE_WRITE_MASK | RXE_SEND_MASK),
};

#define OPCODE_NONE (-1)
#define RXE_NUM_OPCODE (256)

struct rxe_opcode_info {
    char *name;
    enum rxe_hdr_mask mask;
    int length;
    int offset[NUM_HDR_TYPES];
};

extern struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE];
#endif
